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    • 专利摘要:
    An image sensor having a portion comprising interconnect levels formed on a semiconductor substrate (1) covered with a first layer of a dielectric material, comprising conductive tracks (15-1, 15-2 , 15-3) separated from each other by insulating layers (6-1, 6-2, 6-3, 6-4) interconnected by vias (16-1, 16-2, 16-3 ) passing through the insulating layers, and an infrared bandpass filter comprising filter levels adjacent to the interconnect levels formed by an alternation of second layers (6-1, 6-2, 6-3) of the dielectric material , and silicon layers (5-1, 5-2, 5-3), the refractive index of the dielectric material being less than 2.5 at the maximum transmission wavelength of the filter, one of the second dielectric layers of each filter level being identical to the insulating layer of the adjacent interconnection level.
    公开号:FR3036849A1
    申请号:FR1554830
    申请日:2015-05-28
    公开日:2016-12-02
    发明作者:Laurent Frey；Michel Marty；Lilian Masarotto
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] B14127 - DD15286JB 1 METHOD FOR PRODUCING AN INFRARED FILTER ASSOCIATED WITH AN IMAGE SENSOR Domain The present application relates to a method for producing an infrared filter associated with an image sensor. DISCUSSION OF THE PRIOR ART Here, image sensors consisting of a matrix of pixels are considered. Figure 1 schematically shows three pixels of a pixel array of a conventional color image sensor. On a semiconductor substrate 10 are formed pixels of different colors, in the example shown a blue pixel 12B, a green pixel 12G and a red pixel 12R. Each pixel comprises a photodetection zone 14B, 14G, 14R formed in the substrate 10. Charge transfer elements 16B, 16G, 16R, in the illustrated example of the MOS transistors, are provided. The photodetection zones are isolated from each other by insulating trenches 18 formed in the substrate 10. Above the substrate 10 is provided a stack of interconnection levels comprising metal tracks 20 embedded in an insulating material 22. Filters 24B, 24G, 24R are formed on the surface of the stack of interconnection levels and are covered with microlenses 25. Also sometimes provided pixels having filters selecting a band in the field of red or yellow. near infrared, especially in a wavelength range between 600 nm and 1100 nm, for example for distance measurements between the sensor and an object, in which case the bandwidth must be narrow to suppress the signal coming from the scene. Furthermore, it is known that interference filters can be obtained by successive deposition of alternating dielectric layers of low and high optical indices. The number of alternating layers and their thicknesses determine the properties of the filter. As shown in FIG. 2 which corresponds to FIG. 10 of US Pat. No. 5,398,133, an infrared bandpass filter has been made by the combination of a high pass filter 26 and a low pass filter 28. An alternation of layers (26-1 to 26-14) of amorphous silicon (high optical index) and of silicon nitride (low optical index) forms the high-pass filter on a glass support 6. An alternation of layers ( 28-1 to 28-13) of the same materials forms the low-pass filter on the glass support 6.
    [0002] The thickness of each layer is different. This type of filter has the advantage of having a high transmission and a narrow bandwidth. Such filters can be deposited on the surface of the interconnection levels of an image sensor, but do not make it possible to filter a visible band, especially in a wavelength range between 400 nm and 600 nm, in particular. because of the absorption of amorphous silicon. Another disadvantage of the filter described in US Pat. No. 5,398,133 is that it comprises many layers and has a high total thickness. Another disadvantage is that, if such a filter is deposited at the surface of the interconnection levels of an image sensor, the presence of the filter removes all the microlenses of the silicon substrate. It can then be difficult to obtain an effective focus.
    [0003] 3036849 B14127 - DD15286JB 3 Abstract There is a need for an image sensor incorporating filters in the infrared and possibly, in addition, in the visible, of simple structure.
    [0004] Thus, an embodiment provides a method of simultaneously performing a bandpass filter in the infrared of a filter side, and interconnection levels of an interconnection side of an image sensor, comprising the following steps: a) forming a first layer of a dielectric material of refractive index less than 2.5 at the maximum transmission wavelength of the filter on a semiconductor substrate; b) depositing an etch stop layer; C) depositing at least one silicon layer of a first thickness; d) removing, on the interconnection side, said at least one silicon layer; e) depositing a second layer of the dielectric material 20 of a second greater thickness than the first thickness; f) forming in the second layer metal tracks and interconnecting vias, on the interconnection side; g) flattening the surface to a level corresponding to the level of the surface of the second layer, where the second layer does not cover said at least one layer of silicon; and h) repeating steps b) to g) at least once, the values of the first and second thicknesses being selected from one repetition to another, based on calculations involving a simulation step and / or performance electrical appliances. According to one embodiment, the silicon is amorphous silicon. According to one embodiment, the dielectric material 35 is silicon oxide.
    [0005] According to one embodiment, the first and second layers and the silicon layer are deposited at a temperature of between 350 ° C. and 400 ° C. According to one embodiment, the first and second layers and the silicon layer are deposited at the same temperature. According to one embodiment, the method further comprises the step of removing the etch stop layer from the filter side before proceeding to step c).
    [0006] According to one embodiment, said at least one silicon layer comprises an alternation of amorphous silicon layers and silicon oxide layers. According to one embodiment, the etch stop layer is silicon nitride, SiCH, or SiOCH.
    [0007] According to one embodiment, the method further comprises forming, prior to step b), an electrical connection with an element of the semiconductor substrate or with a gate of a field effect transistor formed on the semiconductor substrate. An embodiment also provides an image sensor having a portion comprising: interconnect levels formed on a semiconductor substrate covered with a first layer of a dielectric material, comprising conductive tracks separated from one another by insulating layers, interconnected by vias through the insulating layers; and an infrared bandpass filter comprising filter levels adjacent to the interconnect levels formed by an alternation of second layers of the dielectric material, and silicon layers, the refractive index of the dielectric material being less than 2.5 at the maximum transmission wavelength of the filter, one of the second dielectric layers of each filter level being identical to the insulating layer of the adjacent interconnection level. According to one embodiment, the sensor comprises, on the surface of said portion of the image sensor and facing the infrared bandpass filter, an alternation of third layers of different optical index materials, adding at least one filter level at the infrared bandpass filter. According to one embodiment, the sensor further comprises at least one optical filter formed by an opaque resin layer at wavelengths of the visible range and transparent to infrared wavelengths, disposed on the surface of said portion. and next to the infrared bandpass filter. According to one embodiment, the sensor comprises at least one optical filter, formed by an alternation of at least partially transparent metal layers and fourth layers of dielectrics, disposed on the surface of said portion of the image sensor and opposite the infrared bandpass filter. According to one embodiment, the sensor further comprises zones dedicated to the visible domain comprising color filters arranged on the surface of said portion of the image sensor. According to one embodiment, the color filters are composed of an alternation of at least partially transparent metal layers and fifth layers of dielectrics. According to one embodiment, the color filters are colored resins. According to one embodiment, the sensor comprises first and second plates, each having a front face and a rear face, the first plate comprising on the side of its rear face a first semiconductor substrate whose first photodetection zone is sensitive to radiation. infrared; the second wafer comprising on the side of its rear face a second semiconductor substrate whose second zone comprises pixels sensitive to radiation in the visible range and whose third zone is transparent to the radiation in the infrared range, at least one of the first wafer or second wafer comprising on the side of its face before a structure comprising the interconnection levels and the filter levels; and the front face of the first wafer being contiguous to the front face of the second wafer, so as to align with the first zone the third zone, the filter levels, the alignment of said filter levels forming a bandpass filter infrared. An embodiment also provides a system comprising: a laser source for projecting infrared radiation onto at least one object; and an image sensor as defined above, adapted to detect the radiation reflected by the object. BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying figures, in which: FIG. illustrates the structure of a conventional color image sensor; Figure 2, described above, is a sectional view of an infrared interference filter; Figures aA through 3J illustrate successive steps of a first embodiment of a method for simultaneously manufacturing interconnect levels and levels of an infrared filter of an image sensor; Figures 4A. 4E illustrate successive steps of a second embodiment of a method of simultaneously manufacturing interconnection levels and levels of an infrared filter of an image sensor; FIGS. 5A to 5E illustrate successive steps of a third embodiment of a method for simultaneously manufacturing interconnection levels and levels of an infrared filter of an image sensor; Figure 6A illustrates a sectional view of an embodiment of an image sensor; Figure 6B is a diagram showing the transmission of the infrared filter shown in Figure aA in different configurations; Figures 7 to 9 show sectional views of other embodiments of an image sensor; Fig. 10 shows a possible application of an embodiment of an image sensor to be illuminated by the back side; and Figure 11 shows, partially and schematically, an embodiment of a distance measuring system. DETAILED DESCRIPTION The same elements have been designated with the same references in the various figures and, in addition, the various figures are not drawn to scale. For the sake of clarity, only the elements that are useful for understanding the described embodiments have been shown and are detailed here.
    [0008] In the following description, when reference is made to absolute position qualifiers, such as the terms "left", "right", or relative, such as "above", "below", or orientation qualifiers, such as the term "vertical", reference is made to the orientation of the figures. Unless otherwise specified, the words "about", "substantially" mean within 10%, preferably within 5%. FIGS. 3A to 3J illustrate steps of a first embodiment of a method for simultaneously manufacturing an alternation of layers forming, on the one hand, interconnection levels (left side of the figures) and, on the other hand, an infrared filter (right side of the figures). This method applies in particular to the case where it is desired to produce an image sensor whose structure comprises at least one pixel dedicated to the infrared. The following description will be made in the particular case where a semiconductor substrate 1 has previously been coated with an insulating layer 2, for example made of silicon oxide (SiO 2), in which an electrical connection 3 with an element of the semiconductor substrate 1 or a MOS transistor gate has been prepared.
    [0009] In a first step illustrated in Figure aA, an etch stop layer 4-1 was deposited on the SiO 2 layer. In the step of FIG. 3B, the etch stop layer 4-1 is removed from the right side so that it covers the SiO 2 layer only on the left side.
    [0010] In the step of FIG. 3C, a layer 5-1 of amorphous silicon (a-Si) of thickness e1 has been deposited. In the step of FIG. 3D, the 5-1 layer of a-Si on the left side was etched off to cover the SiO 2 layer only on the right side.
    [0011] In the step of FIG. 3E, a layer 6-1 of a dielectric material having a low refractive index at the wavelength of 850 nm, in particular having a refractive index less than 2, has been deposited. , 5, preferably less than 2, with a thickness e2 greater than the thickness e1. The dielectric material may be SiO 2 or a low-permittivity dielectric (10w-k), that is to say the relative permittivity of which is less than that of SiO 2 which is about 3.6 to 850 rua, especially an Si-O-based mineral-type material having organic or hydride radicals, as described in EP 1 109 221. The upper surface of the layer 6-1 is designated 7-1, where where this layer 6-1 does not cover any of layers 4-1 and 5-1. In the case where the dielectric material is 5iO 2, the etch stop layer is for example a silicon nitride (SiN) layer. In the case where the dielectric material is a low permittivity material, the etch stop layer is for example a SiCH or SiOCH layer. In the step of FIG. 3F, a portion of the layer 6-1 of 5iO2 forming a recess 10-1 of depth less than e2 has been etched on the left side. At the vertical of the connection 3, a second etch in the recess 10-1 was made up to the etch stop layer 4-1, forming a narrower recess 11-1 than the recess 10-1. It will be understood that several recesses of different shapes and sizes can be made simultaneously. In the step of FIG. 3G, the portion of the etch stop layer 4-1 located at the bottom of the recess 11-1 has been removed, and then a metal 12-1, for example copper, has been deposited. contacting the connection 3 at the bottom of the recess 11-1. In a conventional manner, this deposit may be preceded by the deposition of diffusion barrier layers (not shown), for example Ti, Ta, TiN, TaN layers. In the step of FIG. 3H, a planarization of the structure has been carried out to remove all layers above the surface 7-1. This planarization can be achieved, for example, by a chemical mechanical polishing process (CMP). The metal 12-1 remaining in the recesses 10-1 and 11-1 respectively form a conductive track 15-1 and a via 16-1 connecting the track 15-1 to the connection 3.
    [0012] Alternatively, the formation of the SiO layer 6-1 may comprise successively the deposition of a first SiO 2 sublayer, the deposition of an etch stop layer, for example SiN, and the deposition of a second sublayer of SiO 2. The total thickness of the first SiO 2 sub-layer and the etch stop layer is equal to the desired thickness of the via 16-1 and the thickness of the second SiO 2 sub-layer is equal to the thickness of runway 15-1. This makes it possible to better control the thicknesses of each layer of SiO 2. An example of a method of manufacturing the conductive track 15-1 and the via 16-1 by a method comprising the deposition of several insulating sub-layers is described in patent EP 1 109 221. FIG. 31 illustrates a repetition of the succession of steps of Figures aA to 3E, on the structure of Figure 3H. Thus, the following succession of steps was carried out: deposition of an etch stop layer 4-2 on the layer 6-1; 3036849 B14127 - DD15286JB 10 - removal of the etch stop layer 4-2 on the right side; depositing a layer 5-2 of a-Si with a thickness e12; removal of the layer 5-2 from a-Si on the left side; and depositing a layer 6-2 of SiO 2 with a thickness e22 greater than the thickness e12. The upper surface of the layer 6-2 has been designated by the reference 7-2, where this layer 6-2 does not cover any of the layers 4-2 and 5-2. FIG. 3J illustrates the result of the succession of steps of FIGS. 3F to 3H on the structure of FIG. 31.
    [0013] Thus, the following succession of steps was carried out: etching in the SiO layer 6-2, on the interconnection side, of a first depth recess less than e22; etching, within the first recess, a second recess in the layer 6-2, narrower than the first recess, to the etch stop layer 4-2; - removal of the portion of the etch stop layer 4-2 at the bottom of the second recess; depositing a metal layer forming, in the recesses, a conductive track 15-2 and a via 16-2 connecting the track 15-2 to the track 15-1; and planarization of the structure at the surface level 7-2. Thus, using common steps, a stack of two interconnection levels on the left side of the figure and a stack of two levels of infrared filter on the right side of the figure were formed. The alternation of layers of SiO 2 and amorphous silicon constitutes an infrared filter whose filtering properties depend on the number of layers and their thicknesses. If a structure with more than two interconnection levels is provided, the process will be repeated and the number of alternating layers of amorphous silicon and 5122 will be increased. Optical simulation software is used to determine the thicknesses of the amorphous silicon layers to form infrared filters with the desired properties, depending on the thicknesses of 5iO 2 optimized to achieve the desired electrical performance, particularly in terms of capacitances. inter-level interference, depending on the achievable interconnect density. Alternatively, if a structure with more than two interconnect levels is provided, an amorphous silicon layer 5 may not be present at each interconnect level. The inventors have demonstrated that, surprisingly, it is possible to obtain an infrared filter having a suitable spectral response, despite the small number of layers of the infrared filter, and despite the specific constraints due to the fact that the infrared filter is performed simultaneously at interconnection levels, in particular the fact that each layer 6-1, 6-2 of SiO 2 has a thickness imposed after planarization by the intended electrical performance of the interconnection levels and that the position of the base of each layer 5-1, 5-2 of a-Si is imposed by the target electrical performance of the interconnection levels. FIGS. 4A to 4E illustrate steps of a second embodiment of a method of simultaneously manufacturing an alternation of layers forming, on the one hand, an infrared filter 20 and, on the other hand, levels of interconnection of an image sensor structure on a semiconductor substrate 1. As illustrated in FIG. 4A, the starting point is a structure identical to that described previously in relation with FIG.
    [0014] In the step of FIG. 4B, a layer 5-1 of amorphous silicon (a-Si) of thickness e1 has been deposited on the etch stop layer 4-1. In the step of FIG. 4C, the following succession of steps has been carried out: etching removal of the 5-1 layer of a-Si from the left side so that it covers the layer 4-1 of stop etching only on the right side, this etching stop layer not being etched; and depositing a layer 6-1 of SiO2 with a thickness e2 greater than el.
    [0015] The upper surface of the layer 6-1 is designated 8-1, where this layer 6-1 does not cover the layer 51 of a-Si. In the step of FIG. 4D, the following succession of steps has been carried out: etching in the layer 6-1 of SiO 2, on the left side, of a first recess of depth less than e 2; etching, inside the first recess and opposite the connection 3, a second recess in the layer 6-1, narrower than the first, to the etch stop layer 4-10 ; - removal of the portion of the etch stop layer 4-1 at the bottom of the second recess; depositing a metal layer forming, in the recesses, a conductive track 15-1 and a via 16-1 connecting the track 15-1 to the connection 3; and planarization of the structure at the surface level 8-1. In the step of FIG. 4E, the succession of steps of FIGS. 4A to 4D is repeated on the structure of FIG. 4D. Thus, the following succession of steps was carried out: deposition of an etch stop layer 4-2 on the layer 6-2 of SiO 2; depositing a layer 5-2 of a-Si with a thickness e12; removal of the layer 5-2 from a-Si on the left side; depositing a layer 6-2 of SiO2 with a thickness e22 greater than the thickness e12. The upper surface of the layer 6-2 has been designated by the reference 8-2, where this layer 6-2 does not cover the layer 5-2 of a-Si; etching in the layer 6-2 of Si02, on the left side, a first recess of depth less than e22; Etching inside the first recess of a second recess in the narrower layer 6-2 than the first to the etch stop layer 4-2; - removal of the portion of the etch stop layer 4-2 at the bottom of the second recess; Depositing a layer of metal forming, in the recesses, a conductive track 15-2 and a via 16-2 connecting the track 15-2 to the track 15-1; and - planarization of the structure at the surface level 8-2.
    [0016] Thus, using common steps, a stack of two interconnect levels on the left side of the figure and a stack of two levels of infrared filter on the right side of the figure were formed. As in the case of Figures aA-3J, if more than two interconnect levels are provided, the process will be repeated and the number of alternating layers of amorphous silicon, SiO 2 and etch stop will be increased. Similarly, simulation software is used to determine the thicknesses of the amorphous silicon layers, as a function of the thicknesses of the SiO 2 layers and of etch stop imposed by the achievement of the interconnection levels, to form infrared filters at the same time. desired properties. As in the case of Figures aA-3J, if there is a structure with more than two interconnect levels, an amorphous silicon layer may not be present at each interconnect level. FIGS. 5A to 5E illustrate steps of a third embodiment of a method of simultaneously manufacturing an alternation of layers forming, on the one hand, an infrared filter and, on the other hand, levels of interconnection of an image sensor structure on a semiconductor substrate 1. As shown in FIG. 5A, one starts from a structure identical to that described above in relation to FIG. In the step of FIG. 5B, instead of depositing a single layer of amorphous silicon (a-Si) as in the case of FIGS. 3C and 4B, an alternation of 20-1 layers of SiO 2 and -If on the etch stop layer 4-1. This layer alternation 20-1 comprises, in the example shown, a layer of SiO 2 21-1, a layer of a-Si 22-1, another layer of SiO 2 23148 and another layer of a-Si 24-1. The alternation 20-1 of layers has a total thickness e3. In the step of FIG. 5C, the following succession of steps has been carried out: removal of the alternation of layers 20-1 from the left side; and depositing a layer 6-1 of SiO2 with a thickness e2 greater than the thickness e3. The upper surface of the layer 6-1 is designated by the reference 8-1, where this layer 6-1 does not overlap with the alternation of layers 20-1.
    [0017] In the step of FIG. 5D, the following succession of steps has been carried out: etching in the layer 6-1 of SiO 2, on the left side, of a first recess of depth less than the thickness e2; etching, inside the first recess and vertically of the connection 3, a second recess in the layer 6-1, narrower than the first, to the etching stop layer 4- 1; - removal of the portion of the etch stop layer 4-1 at the bottom of the second recess; Depositing a metal layer forming, in the recesses, a conductive track 15-1 and a via 16-1 connecting the track 15-1 to the connection 3; and planarization of the structure at the surface level 8-1. In the step of FIG. 5E, the succession of steps of FIGS. 5D to 5D is repeated on the structure of FIG. 5D. Thus, the following succession of steps was carried out: deposition of an etch stop layer 4-2 on the layer 6-1; depositing an alternation of layers 20-2 of SiO 2 and a-Si on the etch stop layer 4-2. This alternation of layers 20-1 comprises, in the example shown, a layer of SiO 2 21-1, a layer of a-Si 22-1, another layer of SiO 2 23-1, and another layer of If 24-1. The alternation of layers 20-1 is of total thickness e32 - removal of the alternation of layers 20-2 on the left side; Depositing a layer 6-2 of SiO 2 with a thickness e 22 greater than the thickness e 32. The upper surface of the layer 6-2 has been designated by the reference 8-2, where this layer 6-2 does not cover the alternation of layers 20-2; 5 - etching in the layer 6-2 of Si02, on the left side, a first recess of depth less than the thickness e32; etching a second recess in the narrower layer 6-2 and located inside the first recess, to the etch stop layer 4-2; Removing the portion of the etch stop layer 4-2 at the bottom of the second recess; depositing a metal layer forming, in the recesses, a conducting track 15-2 and a via 16-2 connecting the track 15-2 to the track 15-1; and planarizing the structure at the surface 8-2. Thus, using common steps, a stack of two levels of interconnection on the left side of the figure and a stack of several levels of infrared filter on the right side of the figure were formed.
    [0018] As in the case of FIGS. AA-3J and 4A-4E, if more than two interconnect levels are provided, the process will be repeated and the number of alternating layers of amorphous silicon, SiO 2 and etch stop will be increased. Simulation software is used to determine the thicknesses of the alternating layers of amorphous silicon and SiO 2, as a function of SiO 2 layer thicknesses and etch stop layers imposed by achieving interconnection levels, to form infrared filters with the desired properties. In the embodiments described above, the deposits of the different layers must be made at a temperature of less than or equal to 400 ° C. in order to avoid damaging the layers forming the interconnections already present. The layers of metal, silicon oxide and amorphous silicon are, for example, made by physical vapor deposition (PVD).
    [0019] Alternatively, the amorphous silicon oxide and amorphous silicon layers may be deposited by plasma enhanced chemical vapor deposition (PECVD). In this case, the deposition temperature of these two alternately stacked materials in the filter must be identical and greater than 350 ° C to bring mechanical, morphological and thermal stability to the stacks. This deposition method is advantageous in the context of a process comprising a final annealing at about 400 ° C. Indeed the inventors have found a tendency to delamination at certain interfaces of a-Si and SiO 2 after annealing at 400 ° C, for filter levels deposited at a temperature below 350 ° C in PECVD. In the embodiments described above, the thicknesses e2, e22 of the SiO2 layers have values substantially between 150 nm and 650 nm. The thicknesses e1, e12, (or e3, e32) of the amorphous silicon layers (or alternating layers of a-Si and SiO2) have values substantially between 50 nm and 200 nm. The etch stop layers have values substantially between 20 nia and 50 rua.
    [0020] The total thickness of a superposition of deposited layers according to an embodiment of the method described above is substantially between 0.5 gm and 10 pin, preferably between 1 gm and 3 gm. Figure 6A. is a sectional view of an image sensor 25 formed on a semiconductor substrate 1 including photodetection areas 100. The substrate is coated with a layer 2 of SiO 2 in which a connection 3 with a semiconductor substrate element 1 or a MOS transistor gate was prepared. A stack of interconnect levels is shown on the left side of the figure and a stack of filter levels is shown on the right side of the figure. These stacks are formed according to a method corresponding to the first embodiment described in relation to Figures aA to 3J. The left-hand side of FIG. 6P corresponds to a stack 35 of four interconnection levels similar to the interconnection levels shown on the left-hand side of FIG. 30. This stack of levels comprises conductive tracks 15-1, 15-2, 15-3 separated from each other by insulating layers 6-1, 6-2, 6-3, 6-4 and interconnected by vias. 16-1, 165 2, 16-3 passing through the insulating layers. As an exemplary embodiment, the last level of interconnection comprises a connection pad 17 projecting from the surface of the upper part of the image sensor. This interconnect configuration has been shown only as an example. Various configurations of interconnection levels are possible. The right side of the figure corresponds to two pixels dedicated to the infrared P1. This side comprises a stack of four filter levels similar to the filter levels shown on the right-hand side of FIG. 3J. This stack of levels comprises alternating insulating layers 2, 6-1, 6-2, 6-3, 6-4 and layers of amorphous silicon 5-1, 5-2, 5-3, 5-4 forming an infrared filter. Conventionally, at least one passivation layer 30 is deposited on the surface of the interconnection and filter levels. The layer 30 is open facing the pad 17. A final annealing, for example 2 hours at 400 ° C in an N2H2 atmosphere, can be performed after the deposition of the layer 30. A resin layer 40 substantially opaque for the light Visible and infrared transparent, commonly referred to as "black resin", has been deposited on the surface of the right passivation layer 30 in the figure, above the stack of filter levels. A microlens 41 is disposed on the resin layer 40, vertically to each photodetection zone 100. Each pixel P1 comprises a photodetection zone, an infrared filter, a black resin layer and a microlens. Fig. 6B is a diagram showing the transmission T of the filter of Fig. 6A, as a function of the wavelength λ. The curve C1 corresponds to the transmission of the black resin-free filter 40 and the curve C2 corresponds to the transmission of the filter in the presence of a black resin layer 40. The black resin 40 makes it possible to eliminate the parasitic transmission. of the filter in the visible range. These curves correspond to the case where the thicknesses of the deposited layers are as follows: layer 2 5-1 6-1 5-2 6-2 5-3 6-3 5-4 6-4 thickness (nm) 390 50 100 50 In this configuration, the transmission peak is at a wavelength of substantially 850 nm and is greater than 80%. The width at half height of this peak is substantially 25 nia. These performances are compatible with the use of the image sensor 10 as a distance sensor implementing a flight time measurement method or TOF (acronym for lime of flight) in which the width at half height of the peak must generally be between 20 nm and 50 nm and the maximum transmission must be greater than 80%.
    [0021] Fig. 7 is a sectional representation of an image sensor formed on a semiconductor substrate 1 including photodetection areas 101, 102, 103 and 104. The left side of the figure, including interconnection levels and a PI pixel equipped with an infrared filter, is identical to the representation of Figure aA (for a single pixel P1). The common elements have the same references and will not be detailed again here. The right part of the figure represents pixels P2, P3, P4, dedicated to the visible, each being provided with a visible domain filter 42, 43, 44 disposed vertically of the photodetection areas 102, 103 and 104. three filters 42, 43, 44 respectively filter the red, green and blue (RGB) colors. These filters are, for example, of the type illustrated in FIG. 4B of Applicant's US Patent Application No. 2012/0085944, and comprising alternating layers of metal sufficiently thin to be transparent and dielectric layers. The dielectric layers are chosen to pass the chosen colors (RGB). A planarization layer 50 sets the surface above the three filters 42, 43, 44 and the black resin layer 40 at a single level. For each of the pixels P1, P2, P3 and P4, a microlens 41 is disposed. on the flat surface formed by the layer 50. According to one embodiment, the black resin layer 40 may be formed after the formation of the filters 42, 43, 44 and the planarization layer 50.
    [0022] FIG. 8 illustrates an alternative embodiment of an image sensor similar to that of FIG. 7, comprising interconnection levels, a pixel dedicated to the infrared and three pixels dedicated to the visible. The elements common to FIGS. 8 and 7 bear the same references and will not be detailed again here. In FIG. 8, the black resin layer 40 of FIG. 7 has been replaced by an infrared filter 45 made by alternating layers of metal and dielectric in the same manner as the filters 42, 43 and 44 of FIG. Advantageously, the filter 45 can be made at least partly simultaneously with the filters 42, 43 and 44. The infrared filter 45 can not perform filtering alone over a reduced frequency range, which is necessary for the use of the image sensor as a distance sensor of the TOF type. Indeed, the filter 45 can not comprise a large number of insulating and metallic layers because the absorption rate of the metal layers can be significant and the thicknesses of the filters 42, 43, 44 and 45 must be equal. This is why the infrared filter 45 must be associated with the infrared filter corresponding to the stack of layers 5-1, 5-2, 5-3 and 5-4 of amorphous silicon and layers 6-1, 6-2 , 6-3 and 6-4 silicon oxide. According to another embodiment, the filter 45 is replaced by an infrared filter comprising alternating layers of 5iO 2 and amorphous Si layers. This advantageously makes it possible to increase the transmission of the infrared filter produced on the passivation layer 30. Preferably, each filter 42, 43 and 44 comprises amorphous silicon layers in addition to the insulating layers. and metal layers, and the infrared filter can be made at least in part simultaneously with the filters 42, 43 and 44, the metal layers being etched above the infrared pixel P1 after each deposition. FIG. 9 illustrates another embodiment of an image sensor similar to that of FIG. 7. The elements common to FIGS. 9 and 7 bear the same references and will not be detailed again here. In FIG. 9, the filters made by alternating layers of metal and dielectrics 42, 43, 44 of FIG. 7 have been replaced by resins 52, 53 and 54 respectively of red, green and blue colors. An image sensor similar to the embodiments of FIGS. 7, 8 or 9 may be provided, in which the layers (40 or 45) deposited on the surface of the passivation layer 30 and facing the infrared bandpass filter are replaced by alternating layers of amorphous silicon, silicon oxide layers and, in one embodiment, etch stop layers. This alternation forms at least one filter level similar to the filter levels fabricated according to an embodiment of the previously described method which collaborates with these filter levels to form the infrared bandpass filter. Image sensors 25 have heretofore been described comprising a semiconductor substrate, one side of which, called the front face, is coated with an interconnection structure and is intended to receive illumination. Image sensors are also known comprising a semiconductor substrate whose first face, called the front face, is coated with an interconnection structure, and a second face, called the rear face, is intended to receive illumination. This type of structure is commonly used in the art for visible image sensors. Nevertheless, the infrared dedicated photodetection zones require a large semiconductor thickness that is not very compatible with the production of rear-illuminated sensors. FIG. 10 illustrates the combination of a visible-light sensor with back-light illumination and an infrared-illuminated front-panel sensor. For the infrared sensor, the interconnection and filter levels are manufactured according to an embodiment of the previously described method. A first wafer 60 comprises a semiconductor substrate 61 coated with a SiO 2 layer 62 and comprising a photodetection zone 64 dedicated to the infrared. A first interconnection structure 65 has been fabricated according to an embodiment of the method described above, comprising interconnection levels 66 and first levels of infrared filter 67. The infrared filter levels 67 are arranged opposite the zone. 64. A second wafer 70 comprises a thinned semiconductor substrate 71 comprising photodetection areas 72, 73, 74 dedicated to the visible and in configuration for illumination by the rear face, as well as a transparent free space 75. In one embodiment, the free space 75 advantageously corresponds to a region of the semiconductor substrate 71. This second wafer 70 comprises a second interconnection structure 76, contiguous, for example by molecular bonding, to the first structure of the 65. The second structure 76 is manufactured according to an embodiment of the method described above and comprises 77 and second levels of infrared filter 78. This structure is arranged on the lower face side of the thinned semiconductor substrate 74. Each photodetection zone is coated with a color filter 81, 82, 83, forming P7, P8, P9 pixels dedicated to visible. The free space 75 is located opposite the second filter levels 78, and is coated with a black resin layer 84. The second filter levels 78 are aligned and co-operate with the first infrared filter levels 67 for 3036849 B14127 - DD15286JB 22 form a single infrared bandpass filter. The alignment of the free space 75, the black resin 84, the filter levels 67, 78 of the two contiguous structures, with the photodetection zone 64 forms a pixel P10 dedicated to the infrared. This pixel P10 is similar to the infrared pixels of the previously described embodiments. Alternatively, the black resin layer 84 is not present. In this case, the semiconductor substrate 71 may be thicker at the zone 75 so as to form a flat surface with the color filters 81, 82, and 83. This advantageously makes it possible to increase the absorption of the visible spectrum at the pixel P10. In the present embodiment, an infrared filter level 67, 78 is formed in each wafer 60, 70. Alternatively, an infrared filter level can be realized only in one of the wafers 60 or 70. This reduces the number of steps in the sensor manufacturing process. However, the spectral response obtained from the infrared filter may then be less favorable than that obtained with the two levels of infrared filter 67, 78. This combination thus forms an image sensor 20 comprising visible pixels P7, P8, P9 intended for the visible. to be illuminated by the back side and a pixel P10 dedicated to infrared to be illuminated by the front panel. In practice, such configurations are periodically repeated and form a pixel array of an image sensor.
    [0023] FIG. 11 shows a distance measuring system 85 comprising an image sensor 86, as previously described, a projector 87 (Laser), for example a laser source, and a processing module 88 (Processing). Unit) connected to the laser source 87 and the image sensor 86. The processing module 88 may include a processor adapted to execute a computer program stored in a memory. The operating principle of the system 85 is as follows. The laser source 87 emits radiation 89 at the wavelength of the infrared filter of the image sensor 86. The incident radiation 89 is reflected on an object 90. The image sensor 86 detects the radiation 3036849 B14127 - DD15286JB 23 Reflected 91. According to one embodiment, the processing module 88 is adapted to determine the time that the radiation takes to make the path between the object 90 and the image sensor 86. This measurement of flight time can be carried out independently by each pixel of the image sensor, thereby obtaining a complete three-dimensional image of the object 90. According to another embodiment, the laser source 87 is adapted to project a pattern or several patterns on the object and the image sensor 86 is adapted to acquire images of the object 90 on which the patterns are projected. The processing module 88 is adapted from an analysis of the acquired images to determine a three-dimensional image of the object 90. Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, the exemplary embodiments shown in FIGS. 7, 8 and 9 may be manufactured according to the second embodiment of the method described above in relation with FIGS. 4A. 4E, according to the third embodiment of the method described above in relation to FIGS. 5A to 5E, or alternatively according to a combination of the first, second and third embodiments of the method described above. Amorphous silicon deposits have been described to make the infrared filter, it will be understood that instead of amorphous silicon, layers of polycrystalline silicon may be deposited. It is also possible to deposit an antireflection layer composed of a layer of SiO 2 and a layer of SiN between the semiconductor substrate 1 and the layer 2 of 5iO 2. The thicknesses of these layers may be, for example, substantially 25 nm for 5102 and substantially 50 nm for SiN. In the embodiments set forth in FIGS. 6, 7, 8, 9 and 10, it will be understood that the pixels formed by the photodetection areas and the associated filters will be able to form a pixel array according to a periodic repetition of a given pattern, such as for example a Bayer matrix.
    [0024] It will be understood that the interconnections are associated with the photodetection areas of the substrates, and that the connections 17 may be arranged on the surface around the pixel matrix. Those skilled in the art may combine various elements of the various embodiments and variants described above without demonstrating inventive step.
    权利要求:
    Claims (18)
    [0001]
    REVENDICATIONS1. A method of simultaneously providing a bandpass filter in the infrared of a filter side, and interconnection levels of an interconnection side of an image sensor, comprising the steps of: a) forming a first layer (2) of a dielectric material of refractive index less than 2.5 at the maximum transmission wavelength of the filter on a semiconductor substrate (1); b) depositing an etch stop layer (4-1); c) depositing at least one layer of silicon (5-1) of a first thickness; d) removing, on the interconnection side, said at least one layer of silicon (5-1); e) depositing a second layer of the dielectric material (6-1) of a second greater thickness than the first thickness; f) forming in the second layer (6-1) metal tracks (15-1) and vias (16-1) interconnection, the interconnection side; G) flattening the surface to a level corresponding to the level (8-1) of the surface of the second layer, where the second layer does not cover said at least one silicon layer (51); and h) repeating steps b) to g) at least once, the values of the first and second thicknesses being selected from one repetition to another, based on calculations involving a simulation step and / or performance electrical appliances.
    [0002]
    The method of claim 1, wherein the silicon (5-1) is amorphous silicon.
    [0003]
    The method of claim 1 or 2, wherein the dielectric material is silicon oxide.
    [0004]
    The process according to any one of claims 1 to 3, wherein the first and second layers (2,6-1) and the silicon layer (5-1) are deposited at a temperature between 350 C and 400 ° C.
    [0005]
    The method of any one of claims 1 to 4, wherein the first and second layers (2,
    [0006]
    6-1) and the silicon layer (5-1) are deposited at the same temperature. The method of any one of claims 1 to 5, further comprising the step of removing the etch stop layer (4-1) from the filter side prior to proceeding to step c). 10
    [0007]
    The method of any one of claims 1 to 6, wherein said at least one silicon layer comprises an alternation (20-1) of amorphous silicon layers and silicon oxide layers.
    [0008]
    The method of any one of claims 1 to 7, wherein the etch stop layer (4-1) is silicon nitride, SiCH, or SiOCH.
    [0009]
    The method according to any one of claims 1 to 8, further comprising forming, prior to step b), an electrical connection (3) with a semiconductor substrate element (1) or with a gate of a field effect transistor formed on the semiconductor substrate.
    [0010]
    An image sensor having a portion comprising: interconnect levels formed on a semiconductor substrate (1) covered with a first layer of a dielectric material, comprising conductive tracks (15-1, 15-2, 153) separated from each other by insulating layers (6-1, 6-2, 6-3, 6-4), interconnected by vias (16-1, 16-2, 163) passing through the insulating layers ; and an infrared bandpass filter comprising filter levels adjacent to the interconnect levels formed by an alternation of second layers (6-1, 6-2, 6-3) of the dielectric material, and layers of silicon (5-1, 5-2, 5-3), the refractive index of the dielectric material being less than 2.5 at the maximum transmission wavelength of the filter, one of the second dielectric layers of each filter level being identical to the insulating layer of the adjacent interconnection level.
    [0011]
    An image sensor according to claim 10, comprising, on the surface of said portion of the image sensor and opposite the infrared bandpass filter, an alternation of third layers of different optical index materials, adding at least a filter level at the infrared bandpass filter.
    [0012]
    The image sensor according to claim 10, further comprising at least one optical filter formed by a resin layer (40) opaque to visible wavelengths and transparent to infrared wavelengths, disposed on the surface of said portion and facing the infrared bandpass filter.
    [0013]
    An image sensor according to claim 10, comprising at least one optical filter (45), formed by an alternation of at least partially transparent metal layers and fourth layers of dielectrics, disposed on the surface of said sensor portion of the sensor. image and next to the infrared bandpass filter.
    [0014]
    The image sensor according to any one of claims 10 to 13, further comprising areas dedicated to the visible range comprising color filters disposed on the surface of said portion of the image sensor.
    [0015]
    The image sensor of claim 14, wherein the color filters (42,43,44) are composed of alternating at least partially transparent metal layers and fifth layers of dielectrics.
    [0016]
    The image sensor of claim 14, wherein the color filters are color resins (52, 53, 54).
    [0017]
    An image sensor according to claim 10, comprising first and second pads (60,70), each having a front face and a rear face, the first plate (60) comprising on the side of its rear face a first substrate 3036849 B14127 - DD15286JB semiconductor (63) whose first photodetection zone (64) is sensitive to infrared radiation; the second wafer (70) comprising on its rear side a second semiconductor substrate (71) having a second region (72, 73, 74) comprising pixels sensitive to radiation in the visible range and having a third zone (75). is transparent to infrared radiation, at least one of the first wafer or the second wafer having on its front side a structure (65, 76) comprising the interconnection levels (66, 77) and the filter levels (67, 78); and the front face of the first wafer (60) being contiguous with the front face of the second wafer (70), so as to align with the first zone (64) the third zone (75), the filter levels (67) , 78), aligning said filter levels forming an infrared bandpass filter.
    [0018]
    A system (85) comprising: a laser source (87) for projecting infrared radiation (89) onto at least one object (90); and an image sensor (86) according to any one of claims 10 to 17 adapted to detect reflected radiation (91) from the object.
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    同族专利:
    公开号 | 公开日
    EP3098851B1|2021-03-17|
    US9871074B2|2018-01-16|
    FR3036849B1|2018-07-13|
    EP3098851A2|2016-11-30|
    EP3098851A3|2017-02-15|
    US20160351617A1|2016-12-01|
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    法律状态:
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1554830A|FR3036849B1|2015-05-28|2015-05-28|METHOD FOR PRODUCING AN INFRARED FILTER ASSOCIATED WITH AN IMAGE SENSOR|
    FR1554830|2015-05-28|FR1554830A| FR3036849B1|2015-05-28|2015-05-28|METHOD FOR PRODUCING AN INFRARED FILTER ASSOCIATED WITH AN IMAGE SENSOR|
    EP16170357.4A| EP3098851B1|2015-05-28|2016-05-19|Method for producing an infrared filter associated with an image sensor|
    US15/163,557| US9871074B2|2015-05-28|2016-05-24|Method of forming an infrared filter associated with an image sensor|
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